As a new type of flat panel displays, field emission display (FED) is a promising flat panel display following the liquid crystal display (LED) and plasma display panel (PDP). The FED has broad market prospect because of its high resolution, high contrast, wide viewing angle, fast response, high low temperature resistance, shock resistance, low radiation, low production costs, easy realization of digital display.
FED can be simply divided into diode-type and triode type FED according to its structure. The diode-type FED comprises cathode and anode. Electrons are emitted from the cathode under the control of anodic electric field and bombard the phosphor on the anode to emit light. The triod-type FED consists of cathode, gate and anode. Electrons are emitted from the cathode under the control of gate electric field and bombard the phosphor on the anode to realize luminescence.
The manufacturing process for diode-type FED is relatively simple, but high turn-on voltage is needed and uniformity of display is poor. Owing to the voltage limit in circuit, it is difficult to elevate the anode voltage, resulting in lower brightness and poor grayscale reproduction. Therefore, the diode-type FED has many limitations in applications. The triode-type FED, however, is widely used because of its good color purity, high brightness and low drive voltage.
The triode-type FED can be divided into the front-gate, back-gate and planar-gate types according to the position of gate electrode. Due to the small distance between the gate and cathode electrodes, the front-gate-type FED requires low gate voltage without the need high-voltage modulation on anode. But the fabrication process of front-gate structure is complex and it is difficult to achieve large area display as well as emission uniformity. The back-gate FED has a gate electrode buried under the cathode electrode. Electrons are emitted from the materials on the edges of cathodes utilizing the strong electric field between the gate and the cathode edge. However, as the cathode is exposed directly to the anodic electric field, anode voltage should not be too high, otherwise it will give rise to the diode-type emission. In addition, to avoid the crosstalk among the adjacent units, the distance between cathode and anode has to be decreased, which restrict the enhancement of anode voltage. Thus it prevents improving the luminous efficiency of phosphor. In the planar-gate FED, the cathode and gate electrodes are positioned parallelly on a faceplate. The electron emission materials are deposited on the cathodes and the spacing between cathode and gate electrodes is vacuum circumstance. The cathodes and gates can be fabricated simultaneously on the substrate using the normal exposure process and etching technology. In addition, the insulating layer in planar-gate FED is merely distributed in the cross point of the cathode-gate ranks scanning, and dose not influence the gate-controlled properties and electron emission performance. It greatly reduces the complexity and difficulty in manufacturing process. The planar-gate FED is the easiest triode structure to realize large area display because of the simple production process and the cost far less than that of front-gate and back-gate structures.
While there are a large number of patents concerning the structure of FED panel, the drive circuit designed for given structures is less proposed. The drive circuit is an important part of the FED display system, determining largely the performance of FED monitors.